1. Field of the Invention
The following invention relates generally to network semiconductor chips and specifically to sleep mode circuitry in semiconductor chips.
2. Related Art
In recent times, conservation of energy to semiconductor chips has become increasingly important. In fact, it is a standard feature that three power modes are provided: a select (or on) state, a deselect (or off) state, and a sleep mode state. In the sleep mode, the energy of the chip is conserved from the normal on state. In this sleep mode, while the voltage to the individual transistors is not low enough to lose memory (as when the power is turned off in the deselect state), the voltage is turned down to conserve energy as compared to the select state. The power conservation function of the sleep mode is especially important for portable devices, such as laptop computers.
One concern for chip designers is to decrease the leakage current across the individual transistors in the sleep mode. For a typical semiconductor chip, an external power supply supplies on the order of a few volts of power (e.g., 2.5 to 3 volts) to the chip. This external voltage is fed to regulators, and scaled down in power to one or more actual (internal) voltages used by the internal memory devices of the chip. At the present generation of technology, an internal voltage of approximately 1.9 volts is considered standard.
With a high density memory chip, typically millions of transistors are arranged in memory cells, with word lines, plate lines and bit lines used for reading and writing to these memory cells. These memory cells are supplied by the internal voltages.
Unfortunately, each of these transistors leak a small amount current when the chip is in the deselect or sleep mode states. In the sleep mode state, the leakage is on the order of a few picoamps for example. Although the leakage current for each transistor is negligible, the amount of leakage is significant when the tremendous number of transistors is taken into consideration.
To reduce the leakage while in the sleep mode, it is possible to turn off the outputs from a number of the regulators. However, this does not solve the problem because the amount of internal voltage is not reduced, causing the same amount of leakage current to be drawn in the arrays of memory cells.
A number of techniques have been used to decrease the leakage current. One technique has been to change the physical characteristics of individual transistors and memory cells. For example, is possible to raise the threshold voltage for the transistors and/or increase the device lengths (channel lengths) of the transistors. This technique has the disadvantage of deleteriously affecting active-mode (on state) chip performance, and possibly increasing the size of the chip. In addition, these changes would be fixed and permanent.
Another technique has been to add threshold implants (i.e., implant more atoms). This can deleteriously impact the physical characteristics of the transistors when the chip is returned to the on state. Again, these changes would be fixed and permanent.
Another technique is to add additional circuit elements, to block the flow of currents unneeded in the sleep mode, such as turning off redundant charge pumps. For example, specially tailored transistors can be used, which would receive signals to restrict the flow of current during sleep mode. Unfortunately, this technique can adversely impact chip performance and can add additional process steps. In addition, it would provide a fixed and permanent change to the chip as well.
What is needed is a method for decreasing the leakage current by lowering the internal voltage. In particular, what is needed is to lower the leakage current without the disadvantages of prior techniques, such as affecting the size and shape of the transistors, adding implants, or selectively disabling chip subsystems.